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high current driver amplifier and digital vga/preamplifier with 3 db steps data sheet ad8260 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2008C2016 analog devices, inc. all rights reserved. technical support www.analog.com features high current driver differential inputdirect drive from dac preset gain: 1.5 ?3 db bandwidth: 195 mhz large output drive: >300 ma vga/preamplifier low noise voltage noise: 2.4 nv/hz current noise: 5 pa/hz ?3 db bandwidth: 230 mhz gain range: 30 db in 3 db steps ?6 db to +24 db (for preamplifier gain of 6 db) single-ended preamplifier input and differential vga output supplies: 3.3 v to 10 v (with vmid enabled) 3.3 v to 5 v (with vmid disabled) power: 93 mw with 3.3 v supplies power-down for vga, driver amplifier, and system applications digital agc systems tx/rx signal processing power line transceivers functional block diagram 32 2 3 6 31 30 1.5k ? 1k? 29 28 27 26 25 1k? 1.5k ? gm high current driver 9 24 23 22 21 vmid 4 1 ad8260 vmdo txen vmdi vncm vpsb enbl vgap vgan vngr vpsr gns3 gns2 gns1 gns0 prao vngr v ocm inpp inrp inrn inpn txfb v neg v neg txop txop vpos vpos vpsr vmdo prai fdbk 07192-001 5 7 8 10 11 12 13 14 16 15 17 18 19 20 bias vga/preamplifier attenuator gm stages logic 1 +? figure 1. functional block diagram general description the ad8260 includes a high current driver, usable as a transmitter, and a low noise digitally programmable variable gain amplifier (dga), useable as a receiver. the receiver section consists of a single-ended input preampli- fier, and linear-in-db, differential-output dga. the receiver has a small signal C3 db bandwidth of 230 mhz; the driver small signal bandwidth is 195 mhz. the driver delivers 300 ma, well suited for driving low impedance loads, even when connected to a 3.3 v supply. the ad8260 dga is ideal for trim applications and has a gain span of 30 db, in 3 db steps. excellent bandwidth uniformity is maintained across the entire frequency range. the low output- referred noise of the dga is advantageous in driving high speed adcs. the differential output facilitates the interface to modern low voltage high speed adcs. single-supply and dual-supply operation makes the part versatile and enables gain control of negative-going pulses, such as those generated by photodiodes or photo-multiplier tubes, as well as processing band-pass signals on a single supply. for maximum dynamic range, it is essential that the part be ac-coupled when operating on a single supply. the ad8260 preamplifier (pra) is configured with external resistors for gains greater than 6 db and can be inverting or noninverting. the dga is characterized with a noninverting preamplifier gain of 2. the attenuator has a range of 30 db and the output amplifier has a gain of 8 (18.06 db). the lowest noninverting gain range is ?6 db to +24 db and shifts up with increased preamplifier gain. the gain is controlled via a parallel port (pin gns0 to pin gns3) with 10 gain steps of 3 db per code. the preamplifier and dga are disabled for any code that is not assigned a gain step. the ad8260 can operate with single or dual supplies from 3.3 v to 5 v. an internal buffer normally provides a split supply reference for single-supply operation; an external reference can also be used when the vmid buffer is shut down. the operating temperature range is ?40c to +105c. the ad8260 is available in a 5 mm 5 mm, 32-lead lfcsp.
ad8260 data sheet rev. b | page 2 of 32 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? test circuits ..................................................................................... 16 ? theory of operation ...................................................................... 20 ? overview ...................................................................................... 20 ? high current driver amplifier ................................................ 21 ? precautions to be observed during half-duplex operation ....................................................................................................... 22 ? vmid buffer ............................................................................... 22 ? preamplifier ................................................................................. 22 ? preamplifier noise ...................................................................... 22 ? dga ............................................................................................. 23 ? gain control ............................................................................... 23 ? output stage ................................................................................ 23 ? attenuator.................................................................................... 23 ? single-supply operation and ac coupling ........................... 24 ? power-up/power-down sequence .......................................... 24 ? logic interfaces ........................................................................... 24 ? applications information .............................................................. 25 ? evaluation board ............................................................................ 26 ? connecting the evaluation board ............................................ 27 ? outline dimensions ....................................................................... 32 ? ordering guide .......................................................................... 32 ? revision history 5/16rev. a to rev. b change cp-32-8 to cp-32-21 ...................................... throughout updated outline dimensions ....................................................... 32 changes to ordering guide .......................................................... 32 2/11rev. 0 to rev. a added epad notation .................................................................... 7 changes to figure 70 ...................................................................... 29 5/08revision 0: initial version
data sheet ad8260 rev. b | page 3 of 32 specifications v s (supp ly voltage) = 3.3 v, t a = 25c, p r eamplifier g ain = 2 (r fb1 = r fb2 = 100 ?), v vmdo = v s /2 , f = 10 mhz, c l = 5 p f, r l oad = 500 ?, dga differential output . a ll dbm values are referenced to 50 ?, gain code 1011 , unless otherwise spec i fied. table 1 . parameter test conditions /comments min typ max unit driver amp lifier general parameters ? 3 db small signal bandwidth v out = 10 mv p - p, r l oad = 500 ? 19 5 mhz v out = 10 mv p - p, r l oad = 50 ? 120 mhz v out = 10 mv p - p, r l oad = 10 ? 85 mhz ? 3 db large signal bandwidth v out = 1 v p - p 1 95 mhz v out = 2 v p - p 1 90 mhz v out = 2 v p - p , r l oad = 50 ? 1 80 mhz slew rate v out = 1 v p - p 730 v/s v out = 2 v p - p 725 v/s v out = 2 v p - p , r l oad = 50 ? 620 v/s gain nominal gain with internal gain setting resistors 3.0 3.52 db input voltag e noise f = 10 mhz 9.5 nv/hz noise figure r s = 100 ? ( d ifferential, 2 50 ? that convert differential dac output currents to differential voltage) 17.6 db output - referred noise gain = 3.52 db (1.5 ), includes internal gain setting resistors 14.3 nv/hz output impedance dc to 10 mhz , v s = 3.3 v 1.7 ? output current r l oad = 1 ?, v in = 0.5 v 310 ma output signal range r l oad 500 ? v mdo 1.5 v v s = +5 v v mdo 2.3 v v s = 5 v 4.7 v input signal range d iff erential input signal 2 v p - p output offset voltage gain = 3.52 db (1.5) , m ax imum and min imum limits are 3 ?20 5 +20 mv driver amplifier dynamic performance harmonic distortion v out = 1 v p - p hd2 f = 1 mhz ? 84 dbc hd3 ? 85 dbc hd2 f = 10 mhz ? 83 dbc hd3 ?7 0 dbc harmonic distortion v out = 2 v p - p hd2 f = 1 mhz ? 78 dbc hd3 ?7 6 dbc hd2 f = 10 mhz ? 70 dbc hd3 ?5 8 dbc input 1 db compression point 1 3 dbm m ulti tone power ratio (m tpr , in - band) r l oad = 50 ?, v out = 1.4 v p - p max, 10 t ones , 2 mhz to 22 mhz with missing tone at 12 mhz (spacing 2 mhz) ?49 dbc r l oad = 50 ?, v out = 1.4 v p - p max, 16 t ones , 2 mhz to 38 mhz with missing tones at 10 mhz , 20 mhz , 30 mhz , and 40 mhz (spacing 2 mhz) ?43 dbc two - tone intermodulation distor tion (imd3) v out = 1 v p - p, f 1 = 10 mhz, f 2 = 11 mhz ? 90 dbc v out = 2 v p - p, f 1 = 10 mhz, f 2 = 11 mhz ?7 1 dbc v out = 1 v p - p, f 1 = 45 mhz, f 2 = 46 mhz ?6 0 dbc v out = 2 v p - p, f 1 = 45 mhz, f 2 = 46 mhz ? 48 dbc output third - order intercept v out = 1 v p - p, f = 10 mhz 4 3 dbm v out = 2 v p - p, f = 10 mhz 40 dbm v out = 1 v p - p, f = 45 mhz 28 dbm v out = 2 v p - p, f = 45 mhz 28 dbm two - tone intermodulation distortion (imd3), r l oad = 50 ? v out = 1 v p - p, f 1 = 10 mhz, f 2 = 11 mhz ? 69 dbc v out = 2 v p - p, f 1 = 10 mhz, f 2 = 11 mhz ?7 2 dbc v out = 1 v p - p, f 1 = 45 mhz, f 2 = 46 mhz ?5 1 dbc v out = 2 v p - p, f 1 = 45 mhz, f 2 = 46 mhz ? 48 dbc
ad8260 data sh eet rev. b | page 4 of 32 parameter test conditions /comments min typ max unit output third - order intercept, r l oad = 50 ? v out = 1 v p - p, f = 10 mhz 3 3 dbm v out = 2 v p - p, f = 10 mhz 4 0 dbm v out = 1 v p - p, f = 45 mhz 2 3 dbm v out = 2 v p - p, f = 45 mhz 28 dbm preamplfier and vga general parameters ? 3 db small signal bandwidth v out = 10 mv p - p , gain code = 0110 23 0 mhz ? 3 db large signal bandwidth v out = 1 v p - p , gain code = 0110 165 mhz v out = 2 v p - p , gain code = 0110 135 mhz slew rate v out = 1 v p - p , gain code = 0110 330 v/s v out = 1.6 v p - p , gain code = 0110 335 v/s input voltage noise f = 10 mhz (short ed input ) 2.4 nv/hz f = 10 mhz (input open) 6.2 nv /hz noise figure max imum g ain ( gain c ode = 1011), r s = 50 ?, unterminated 10.2 db max imum gain ( gain c ode = 1011), r s = 50 ?, shunt terminated with 50 ? 15.5 db output - referred noise max imum gain ( gain c ode = 1011), g ain = 24 db (input short) 38 nv/hz max imum gain ( gain c ode = 1011), g ain = 24 db (input open) 98.1 nv/hz min imum gain ( gain c ode = 0001), g ain = ? 6 db 25 nv/hz output impedance dc to 10 mhz 3 ? output signal range (per pin ) r l oad 500 ? v mdo 0.7 v v s = +5 v v mdo 1.4 v v s = 5 v 3.6 v input signal range preamplifier input v mdo 0.3 v output offset voltage max imum gain ( gain code = 1011), gain = 24 db , 3 limits ?50 20 +50 mv preamplifier and vga dynamic performance har monic distortion gain c ode = 0110, gain = 9 db, v out = 1 v p - p hd2 f = 1 mhz ?90 dbc hd3 ?87 dbc hd2 f = 10 mhz ?75 dbc hd3 ?58 dbc harmonic distortion gain c ode = 1011, gain = 24 db, v out = 2 v p - p hd2 f = 1 mhz ?94 dbc hd3 ?9 0 dbc hd2 f = 10 mhz ?61 dbc hd3 ?84 dbc input 1 db compression point min imum gain ( gain code = 0001), gain = ?6 db (preamplifier limited) 1.9 dbm max imum gain ( gain code = 1011), gain = 24 db (vga limited) ?9.2 dbm mtpr (in - band) v out = 1.4 v p - p max imum , 10 tones, 2 mhz to 22 mhz with missing tone at 12 mhz (spacing 2 mhz) , gain c ode = 1011, gain = 24 db ?68 dbc v out = 1.4 v p - p max imum , 16 tones, 2 mhz to 38 mhz with missing tones at 10 mhz, 20 mhz, 30 mhz, and 40 mhz (spacing 2 mhz ) ?61 dbc two - tone intermodulation distortion (imd3) gain c ode = 1011, gain = 24 db v out = 1 v p - p, f 1 = 10 mhz, f 2 = 11 mhz ?9 2 dbc v out = 2 v p - p, f 1 = 10 mhz, f 2 = 11 mhz ? 77 dbc v out = 1 v p - p, f 1 = 45 mhz, f 2 = 46 mhz ? 50 dbc v out = 2 v p - p, f 1 = 45 mhz, f 2 = 46 mhz ? 36 dbc output third - order intercept gain c ode = 1011, gain = 24 db v out = 1 v p - p, f = 10 mhz 4 4 dbm v out = 2 v p - p, f = 10 mhz 4 3 dbm v out = 1 v p - p, f = 45 mhz 2 7 dbm v out = 2 v p - p, f = 45 mhz 22 dbm
data sheet ad8260 rev. b | page 5 of 32 parameter test conditions /comments min typ max unit overload recovery max imum gain ( gain code = 1011), gain = 24 db, v in = 50 m v p - p to 500 mv p - p 50 ns group delay variation 1 mhz < f < 50 mhz, full gain range 2 ns accuracy absolute gain error all gain codes , limits are 3 ?0. 5 0. 1 5 +0. 5 db gain law conformance (dnl) differential gain error , code to code ?0.3 0.15 +0.3 db gain control gain step per code 3.0 db gain range default = ?6 db to +24 db 30 db response time 30 db gain change ( gain code stepped from 0001 to 101 1) 50 ns logic interfaces high level input voltage 1.4 v s v low level input voltage 0 0.8 v logic input bias current logic high, v logic = 3.3 v 0.2 a logic low 18 na power supply supply voltage s ingle supply 3.3 10 v dual su pply 3.3 5 v quiescent current full chip enabled (txen = 1, enbl = 1, gain code = 0001) 28. 3 ma txen = 0, enbl = 1, gain code = 0001, driver off, dga on 19 .1 ma txen = 1, enbl = 1, gain code = 0000, driver on, dga off 10.8 ma chip disabled (txen = 0, enbl = 0, gain code = 0000) 35 a v s = 5 v, no signal 34.2 ma psrr max imum gain ( gain code = 1011), gain = 24 db, 1 mhz ?30 db driver amplifier, 1 mhz ?48 db power dissipation no signal 93 mw no signal, v pos ? v neg = 10 v 3 42 mw enable times chip enable time bias only , txen = 0, gain code = 0000, enbl = 0 to 1 0.4 s all at once , txen = 0 to 1, gain code = 0000 to 0001, enbl = 0 to 1 0.3 s preamplifier and dga enable time enbl = 1, txen = 0, gain code = 0000 to 0001 0.3 s driver enable time enbl = 1, gain code = 0001, txen stepped from 0 to 1 0.2 s disable times chip disable time txen = 1 to 0, gain c ode = 0001 to 0000, enbl = 1 to 0 , i s upply = 100 a 20 s all at once , txen = 1 to 0, gain cod e = 0001 to 0000, enbl = 1 to 0 , i s upply = 35 a 50 s preamplifier and dga disable time enbl = 1, txen = 0, gain code = 0001 to 0000 0.4 s driver disable time enbl = 1, gain code = 0000, txen = 1 to 0 2.2 s
ad8260 data sheet rev. b | page 6 of 32 absolute maximum ratings table 2. parameter rating voltage supply voltage (vpos, vneg) 6 v input voltage (inxx, prai, fdbk, vmdi, vocm) vpos, vneg logic voltages vpos, ground temperature operating temperature range C40c to +105c storage temperature range C65c to +150c lead temperature (soldering, 60 sec) 300c thermal data 1 maximum junction temperature 125c ja 47.3c/w jc 6.9c/w jb 28.6c/w jt 0.6c/w jb 27.4c/w 1 thermal data at zero airflow with exposed pad soldered to four-layer jedec board with vias per jesd51-5. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution
data sheet ad8260 rev. b | page 7 of 32 pin configuration and fu nction descriptions 07192-002 vpsr fdbk prai vmdo vpos vpos txop txop inpn vneg vneg txfb inrn inrp inpp vocm pin 1 indicator vmdo notes 1. the exposed pad is not connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the ground plane. the ground plane pattern should include a pattern of vias to inner layers. txen vmdi vncm vpsb enbl vgap vgan vngr vpsr gns3 gns2 gns1 gns0 prao vngr 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 ad8260 top view (not to scale) figure 2. pin configuration table 3. pin function descriptions pin no. mnemonic description 1, 19 1 vmdo vmid buffer output. requires robust ac decoupli ng with a capacitance of 0.1 f capacitor or greater. 2 txen driver enable. logic threshold = 1.1 v with 0.2 v hysteresis. 3 vmdi vmid input voltage. normally decoupled with a 0.1 f capacitor. when pulled to vncm, the vmid buffer shuts down. this can be useful when using th e part with dual supplies or when an external midpoint generator is used. 4 vncm negative supply for bias cell, vmid cell, an d logic inputs. (ground this pin in applications.) 5 vpsb positive supply for bias cell and vmid cell. 6 enbl enable. logic threshold = 1.1 v. when low, the ad8260 is disabled and the supply current is 35 a when txen and all gnsx pins are also low. 7 vgap positive vga output (needs to be ac-coupled for single supply). 8 vgan negative vga output (needs to be ac-coupled for single supply). 9, 16 1 vngr negative supply for preamplifier and dga (set to ?vpos for dual supply; gnd for single supply). 10, 20 1 vpsr positive supply for preampli fier, dga, and gnsx logic decoder. 11 gns3 msb for gain control. logic threshold = 1.1 v. 12 gns2 gain control bit. logic threshold = 1.1 v. 13 gns1 gain control bit. logic threshold = 1.1 v. 14 gns0 lsb for gain control. logic threshold = 1.1 v. 15 prao preamplifier output. 17 fdbk negative input of preamplifier. 18 prai positive input of preamplifier. 21, 22 1 vpos positive supply for driver amplifier. 23, 24 1 txop driver output. 25, 26 1 vneg negative supply for driver amplifier (set to ?vpos for dual supply; gnd for single supply). 27 txfb feedback for driver amplifier. 28 inpn negative driver amplifier input. 29 inrn negative gain resistor input for driver amplifier. 30 inrp positive gain resistor input for driver amplifier. 31 inpp positive driver amplifier input. 32 vocm output common mode pin. normally connected to pin vmdo. epad exposed pad. the exposed pad is not connected internally . for increased reliability of the solder joints and maximum thermal capability it is recommended that the pa d be soldered to the ground plane. the ground plane pattern should include a pattern of vias to inner layers. 1 pins with the same name are connected internally.
ad8260 data sheet rev. b | page 8 of 32 typical performance characteristics v s (supply voltage) = 3.3 v, t a = 25c, c l = 5 pf, f = 10 mhz, preamplifier gain = 2, r fb1 and r fb2 of the preamplifier = 100 , r load of the driver amplifier = 500 , t x and r x enabled, unless otherwise specified. 5 1 0 2 3 4 gain (db) frequency (hz) 200m 100m 10m 1m 100k t = ?40c v out = 200mv p-p t = +105c 07192-003 t= +25c figure 3. small-signal frequency response at three temperatures of the high current driversee figure 51 5 1 0 2 3 4 gain (db) frequency (hz) 200m 100m 10m 1m 100k v s = +5v v out = 200mv p-p v s = +3.3v v s = 5v 07192-004 figure 4. small-signal frequency response of the high current driver for three supply voltagessee figure 51 5 1 0 2 3 4 gain (db) frequency (hz) 200m 100m 10m 1m 100k 07192-005 v load = 1v p-p; r load =50 ? v load = 1v p-p; r load =500 ? v load = 2v p-p; r load =50 ? v load = 2v p-p; r load =500 ? figure 5. large-signal frequency respon se of the high current driver for two values of output voltage and two valu es of load resistancesee figure 51 20 0 5 10 15 noise (nv/ hz) frequency (hz) 50m 10m 1m 100k rto rti 07192-006 figure 6. input-referred and output-referred noise of the high current driversee figure 52 10 output impedance ( ? ) frequency (hz) 100m 10m 1m 100k 100 0.1 1 0 7192-007 figure 7. output impedance of the high current driver see figure 53 ? 100 harmonic distortion (dbc) load resistance ( ? ) 1k 100 10 ?40 ? 20 ?60 ?80 ?90 hd3 hd2 ?70 ?50 ?30 2v p-p 1v p-p 07192-008 figure 8. harmonic distortion (hd2, hd3) vs. load resistance for the high current driversee figure 54
data sheet ad8260 rev. b | page 9 of 32 ?100 harmonic distortion (dbc) load capacitance (pf) 100 40 0 ?40 ? 20 ?60 ?80 ?90 80 2010 60 f = 10mhz ?70 ?50 ?30 50 90 30 70 hd2, v out = 1v p-p hd3, v out = 1v p-p hd2, v out = 2v p-p hd3, v out = 2v p-p 07192-009 figure 9. harmonic distortion (hd2, hd3) vs. load capacitance at two values of output voltage for the high current driversee figure 54 ?100 harmonic distortion (dbc) output voltage (v p-p) 3.0 1.5 0 ?40 ?20 ?60 ?80 ?120 0 2.5 1.0 0.5 2.0 hd3 hd2 f = 10mhz 07192-010 figure 10. harmonic distortion (hd2, hd3) vs. output voltage for the high current driversee figure 54 ?100 harmonic distortion (dbc) frequency (hz) 100m 10m 1m ?40 ? 20 ?60 ?80 ?90 hd3 hd2 ?70 ?50 ?30 1v p-p 2v p-p 07192-011 figure 11. harmonic distortion (hd2, hd 3) vs. frequency of the high current driver at two values of output voltagesee figure 54 100m frequency (hz) 2m imd3 (dbc) 10m ?100 ?80 ?60 ?40 ?20 0 r load = 50 ? , v out = 1v p-p r load = 50 ? , v out = 2v p-p r load = 500 ? , v out = 1v p-p r load = 500 ? , v out = 2v p-p 07192-012 figure 12. imd3 vs. frequency for two values of output voltage and two values of load resistance for the high current driversee figure 55 100m frequency (hz) 2m oip3 (dbm) 10m 50 40 30 20 10 0 r load = 50 ? , v out = 1v p-p r load = 50 ? , v out = 2v p-p r load = 500 ? , v out = 1v p-p r load = 500 ? , v out = 2v p-p 07192-013 figure 13. third-order intercept (oip3) vs . frequency for the high current driver see figure 55 0 20 ip1db (dbm) frequency (hz) 100m 10m 1m 5 15 10 r load = 50 ? r load = 500 ? 07192-014 figure 14. input-referred 1 db compression (ip1db) vs. frequency for two values of load resistance for the high current driver
ad8260 data sheet rev. b | page 10 of 32 ?80 frequency (mhz) 2422 18 210 0612 42 0 1614 0 8 output (dbm) ?60 ?40 ?90 ?70 ?20 ?50 ?30 ?10 07192-015 figure 15. missing tone power ratio for the high current driver 0 0.15 ?0.15 0 .05 0.10 output voltage (v) time (ns) 80 70 60 ?0.05 ?0.10 ?20 10 ?30 0 30 ?10 20 5040 ?0.20 0.20 r load = 10 ? r load = 50 ? r load = 100 ? r load = 500 ? c load = 5pf noninverting 07192-016 figure 16. small-signal pulse response of the high current driver for various values of load resistance, r load see figure 56 0 0.15 ?0.15 0.05 0.10 output voltage (v) time (ns) 807060 ?0.05 ?0.10 ?20 10 ?30 0 30 ?10 20 5040 ?0.20 0.20 c load = 5pf c load = 47pf c load = 10pf r load = 500 ? noninverting 07192-017 figure 17. small-signal pulse response of the high current driver for various values of load capacitance, c load , and r load = 500 ?see figure 56 0 0.15 ?0.15 0.05 0.10 output voltage (v) time (ns) 807060 ?0.05 ?0.10 ?20 10 ?30 0 30 ?10 20 5040 ?0.20 0.20 c load = 5pf c load = 47pf c load = 10pf r load = 50 ? noninverting 07192-018 figure 18. small-signal pulse response of the high current driver for various values of load capacitance, c load , and 50 loadsee figure 56 output voltage (v) time (ns) 807060 20 10 30 0 30 10 20 5040 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 r load =10 ? r load = 50 ? r load =100 ? r load = 500 ? c load =5pf noninverting 07192-019 figure 19. large-signal pulse response of the high current driver for various values of load resistance, r load see figure 56 0 1.5 ?1.5 0.5 1.0 output voltage (v) time (ns) 807060 ?0.5 ?1.0 ?20 10 ?30 0 30 ?10 20 5040 ?2.0 2.0 c load = 5pf c load = 47pf c load = 10pf r load = 500 ? noninverting 07192-020 figure 20. large-signal pulse response of the high current driver for various values of load capacitance, c load , and r load = 500 ?see figure 56
data sheet ad8260 rev. b | page 11 of 32 output voltage (v) time (ns) c load =5pf c load = 10pf c load = 47pf 807060 ?20 10 ?30 0 30 ?10 20 50 40 r load =50 ? noninverting 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 07192-021 figure 21. large-signal pulse response of the high current driver for various values of load capacitance, c load , and 50 loadsee figure 56 27 24 21 18 15 12 9 6 3 0 ?3 ?6 ?9 gain select code gain (db) 07192-022 10111010100110000111 01100101 0001 010000110010 average of 3 samples f = 1mhz, 10mhz, and 40mhz figure 22. gain vs. gain select code for three samples for the vga/preamplifier at three frequenciessee figure 57 4.00 3.75 3.50 3.25 3.00 2.75 2.50 2.25 2.00 gain step (db) 07192-023 average of 3 samples f = 1mhz, 10mhz, and 40mhz gain select code 1011 1010 1001 1000 0111 0110 0101 01000011 0010 figure 23. gain step vs. gain select code for three samples for the vga/preamplifier at three frequenciessee figure 57 1.00 0.75 0.50 0.25 0 ?0.25 ?0.50 ?0.75 ?1.00 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 gain select code absolute gain error (db) 07192-024 average of 3 samples f = 1mhz, 10mhz, and 40mhz figure 24. absolute gain error vs. gain select code for three samples for the vga/preamplifier at three frequencies normalized to 1 mhz and code 0110 see figure 57 1.00 0.75 0.50 0.25 0 ?0.25 ?0.50 ?0.75 ?1.00 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 gain select code gain error (db) 07192-025 average of 3 samples at each temperature t = +105c t = +25c t = ?40c figure 25. gain error vs. gain select code at three temperatures for the vga/preamplifiersee figure 57 0 ?40 ?30 ?20 50 20 30 40 ?50 offset voltage (mv) gain select code 101010011000011101100101 0001 010000110010 average of 3 samples at each temperature 1011 10 ?10 t = +105c t = +25c t = ?40c 07192-026 figure 26. output offset voltage vs. ga in select code at three temperatures for the vga/preamplifiersee figure 58
ad8260 data sheet rev. b | page 12 of 32 27 24 21 18 15 12 9 6 3 0 ?3 ?12 ?6 ?9 100k 1m 10m 100m 200m frequency (hz) differential gain (db) 07192-027 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 figure 27. frequency response for a supply voltage (v s ) of 3.3 v for all codes of the vga/preamplifiersee figure 59 27 24 21 18 15 12 9 6 3 0 ?3 ?12 ?6 ?9 100k 1m 10m 100m 200m frequency (hz) differential gain (db) 07192-028 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 v s = 5v figure 28. frequency response for a supply voltage (v s ) of 5 v for all codes for the vga/preamplifiersee figure 59 27 24 21 18 15 12 9 6 3 0 ?3 ?12 ?6 ?9 100k 1m 10m 100m 200m frequency (hz) differential gain (db) 07192-029 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 v s = 5v figure 29. frequency response for a dual supply (v s ) = 5 v for all codes for the vga/preamplifiersee figure 59 10 8 6 4 2 0 1m 10m 100m frequency (hz) group delay (ns) 07192-030 figure 30. group delay vs. frequency for the vga/preamplifier see figure 59 100 output resistance ( ? ) frequency (hz) 100m 0.1 1m 100k 10m vgap 10 1 vgan 0 7192-031 figure 31. output resistance vs. frequency for the vga/preamplifier see figure 60 10 50 20 30 40 gain select code output-referred noise (nv/ 07192-032 figure 32. output-referred noise vs. gain select code for the vga/preamplifiersee figure 61
data sheet ad8260 rev. b | page 13 of 32 10 100 frequency (hz) output-referred noise (nv/ hz) 10m 100k 1m 50m gain code = 1011 07192-033 figure 33. output-referred noise vs. frequency for the vga/preamplifier at maximum gainsee figure 61 1 100 10 gain select code input-referred noise (nv/ hz) 101010011000011101100101 0001 010000110010 1011 07192-034 figure 34. input-referred noise vs. gain select code for the vga/preamplifier see figure 61 1 10 frequency (hz) short-circuit input-referred noise (nv/ hz) 10m 100k 1m 50m gain code = 1011 07192-035 figure 35. short-circuit input noise vs . frequency for the vga/preamplifier see figure 61 50 harmonic distortion (dbc) load resistance ( ? ) 1800 1600 1400 1200 200 1000800 400 0 2000 30 40 60 80 70 600 hd2 hd3 07192-036 v out = 1v p-p gain code = 0110 figure 36. harmonic distortion (hd2, hd3) vs. load resistance for the vga/preamplifiersee figure 62 load capacitance (pf) harmonic distortion (dbc) ?70 ?60 ?50 ?40 ? 30 ?80 10 40 030 20 50 v out = 1v p-p gain code = 0110 hd2 hd3 07192-037 figure 37. harmonic distortion (hd2, hd3) vs. load capacitance for the vga/preamplifiersee figure 62 ?120 harmonic distortion (dbc) gain select code 101010011000011101100101 1011 ?20 ?40 ?60 ?80 ?100 0 measurement of distortion is limited by the maximum dynamic input range of the preamplifier hd2, f c = 1mhz v out = 1v p-p hd3, f c = 1mhz hd2, f c = 10mhz hd3, f c = 10mhz 07192-038 figure 38. harmonic distortion (hd2, hd3) vs. gain select code at 1 mhz and 10 mhz for the vga/preamplifiersee figure 62
ad8260 data sheet rev. b | page 14 of 32 0 ?100 harmonic distortion (dbc) frequency (hz) 100m 10m 1m ?40 ?20 ?60 ?80 ?120 hd2 hd3 gain code = 1011 v out = 1v p-p 07192-039 figure 39. harmonic distortion (hd2, hd3) vs. frequency for the vga/preamplifiersee figure 62 0 ?100 imd3 (dbc) frequency (hz) 100m 10m 1m ?40 ?20 ?60 ?80 ?120 lower upper v out = 1v p-p tones 1mhz apart each tone 0.5v p-p gain code = 1011 07192-040 figure 40. third-order intermodulation distortion (imd3) vs. frequency for the vga/preamplifier 60 10 oip3 (dbm) frequency (hz) 100m 10m 1m 40 50 30 20 0 lower upper gain code = 1011 tones 1mhz apart 07192-041 figure 41. oip3 vs. frequenc y for the vga/preamplifier 10 5 0 ?5 ?10 ?15 ?20 ?25 ?30 gain select code input ip1db (dbm) 101010011000011101100101 0001 010000110010 1011 1mhz 10mhz ip1db limited at low gain by the dynamic range of the preamplifier 07192-042 figure 42. input 1 db compression (ip1db) vs. gain select code at 1 mhz and 10 mhz for the vga/preamplifier 07192-043 ch1 2.00v ? m10.0ns a ch4 180v 1 m t 27.2000ns t math 5.00mv 10.0ns input output 50mv/div 0v 2mv/div 0v figure 43. small-signal pulse response for the vga/preamplifier 07192-044 ch3 20.0mv ? m10.0ns a ch4 200v 3 m t 27.2000ns t math 50.0mv 10.0ns input output 500mv/div 0v 20mv/div 0v figure 44. large-signal pulse response for the vga/preamplifier
data sheet ad8260 rev. b | page 15 of 32 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?3?2?1012345678 time (ns) output voltage (v) 07192-045 v s = +3v, +5v, and 5v figure 45. large-signal pulse response for various values of supply voltage for the vga/preamplifier 07192-046 ch1 1.00v ? ch2 20.0mv ? math 100mv 200nv ch2 20.0mv ? m200ns a ch1 760mv 1 m 4 t 595.200ns ch1 ampl 3.28v ch2 ampl 1.20mv math ampl 117mv t figure 46. gain response for the vga/preamplifier, yellow: gain code select, red: vga differential output, blue/green: vgap and vgan 0 1 output voltage (v) time (ns) 800700600 ?1 ?200 1000 300 ?100 200 500400 ?2 2 07192-047 figure 47. overdrive recovery of the vga/preamplifiergain code = 1011 frequency (hz) psrr (db) 1m 100k 5m ? 10 ?20 ?30 ?40 ?50 ?60 ?70 ?supply high current driver +supply high current driver +supply vga/preamplifier ?supply vga preamplifier v s = 3.3v gain code = 1011 07192-048 figure 48. psrr vs. frequency for dual supplies for the high current driver and the vga/preamplifier quiescent supply current (ma) 0 40 30 ?55 10 temperature ( ? c) 52545 20 65 85 105 125 ?15?35 5 15 35 25 fully enabled vga/preamplifier enabled high current driver enabled 07192-049 figure 49. quiescent supply current vs. temperature for three operating states standby quiescent supply current (a) ?55 ?35 ?15 temperature (c) 5 25 45 65 85 105 125 80 70 60 50 40 30 20 10 0 07192-050 figure 50. standby quiescent su pply current vs. temperature
ad8260 data sheet rev. b | page 16 of 32 test circuits inrp ? + network analyzer vocm 453 ? inrn 50 ? in out 0.1f 5pf 0.1f 50 ? ad8260?high current driver txfb txop vmdo 50 ? 07192-151 figure 51. test circuit for frequency response of the high current driver in 50? inrp ? + vocm inrn 0 .1 f 0 .1 f 0.1f txfb txop ? + vmdo spectrum analyzer 07192-152 ad8260?high current driver figure 52. test circuit for input-referred and ou tput-referred noise of the high current driver network analyzer with s-parameter mode in 50 ? inrp vocm inrn 0.1f 0.1f txfb txop +3.3 v ?3.3v ? + 07192-153 ad8260?high current driver figure 53. test circuit for output im pedance of the high current driver signal generator 50? lp filter in 50? inrp vocm inrn 0.1f 0.1f 0.1f txfb txop vmdo spectrum analyzer 50? 50? r load c load 1:1 07192-154 ad8260?high current driver ? + figure 54. test circuit for harmonic distortion of the high current driver
data sheet ad8260 rev. b | page 17 of 32 signal generators 50? in 50? inrp vocm inrn 0.1f 0.1f 0.1f txfb txop vmdo spectrum analyzer 453 ? 1k? 1k? 1:1 07192-155 ad8260?high current driver 50? ? + figure 55. test circuit for imd3 an d oip3 of the high current driver oscilloscope in 50? 50 ? inrp ? + vocm inrn 0.1f 0.1f 0.1f txfb txop vmdo 50? 12.5 ? r load c load 07192-156 ad8260?high current drive r figure 56. test circuit for pulse re sponse of the high current driver oscilloscope in 50? 50 ? 453? 453? vmdo 0.1f 0.1f 0.1f 100 ? signal generator 50 ? + ? 100 ? preamp 07192-157 ad8260?vga/preamplifie r figure 57. test circuit for gain step size and error of the vga/preamplifier dmm vmdo 0.1f 100? + ? 100? preamp 07192-158 ad8260?vga/preamplifie r figure 58. test circuit for output-referre d offset voltage of the vga/preamplifier
ad8260 data sheet rev. b | page 18 of 32 vmdo 0.1f 100 ? + ? 100 ? preamp in network analyzer 0.1f 453? 0.1f 453? 50? 50? 07192-159 ad8260?vga/preamplifier figure 59. test circuit for frequency response and group delay of the vga/preamplifier +3.3v ?3.3v 0.1 f 100 ? + ? 100 ? preamp in network analyze r with s-parameter capability 50? 07192-160 ad8260?vga/ preamplifier figure 60. test circuit for output resistance of the vga/preamplifier 0.1f 1k? 1k? 100? 100? vmdo vmdo spectrum analyzer 50? + ? preamp vga 0.1f 0.1f 0.1f ad8129 10 07192-051 ad8260?vga/preamplifier figure 61. test circuit for input-referred and output-r eferred noise measurements of the vga/preamplifier
data sheet ad8260 rev. b | page 19 of 32 0.1f 475 ? 475 ? 100 ? 100 ? vmdo + ? preamp 0.1f 0.1f 07192-052 spectrum analyzer 50? 1:1 lp filter 50? 50 ? figure 62. test circuit for harmonic distortion measurements of the vga/preamplifier vmdo 0.1f 100 ? + ? 100 ? preamp oscilloscope 50 ? 50 ? in 50 ? 07192-163 a d8260?vga/preamplifie r figure 63. test circuit for ip1db, pulse response, overdr ive recovery, and gain response of the vga/preamplifier
ad8260 data sh eet rev. b | page 20 of 32 theory of o peration overview th e ad8260 is a self - contained transceiver intended for analog communications using a power line as the media . operating on supplies as low as 3.3 v, i t includes a high current driver usable as a t ransmitter and a low noise digitally programmable variable gain amplif ier (dga), us able as a receiver (see figure 64) . a n uncommitted current - feedback high frequency op amp acts a s a preamplifier and interface to the dga and is use r configured for gains greater than 6 db. combined, the v ga and preamplifier are us able at high signal levels from dc to 100 mhz , with a small - signal ? 3 db bandwidth of 23 0 mhz . to implement a high current - output vga, the vga output can be connected to th e d river - amplifier differential input . the small - signal ? 3 db bandwidth of the driver amplifier is 1 9 5 mhz and the large - signal bandwidth is >115 mhz, even when driving a 50 load. the device is fabricated on the analog devices, inc., high speed (extra f ast complementary bipolar) xfcb proc ess. the pream - plifier and dga feature low dc offset voltage, and a nominal gain range of ? 6 db to + 24 db , a 30 db gain span , and a differential output for adc driving. the power consumption is 93 mw with a single 3.3 v supply. the supply current is typically about 28 ma when all ci rcuits in the device are active. during normal usage, either the driver amp lifier is on or the preamplifier and dga are on and , therefore , the supply current in general is less than 28 ma. the gain of the ad8260 vga is programmed via a 4 - bit parallel interface . figure 64 shows the circui t block diagram and basic application connections , and illustrates the envi sioned external dac, adc, and power - line bus interface connections. the diagram shows the connections for single 3.3 v supply operation ; if a dual supply is available , the vmid generator can be shut down and pin vmdi, pin vmdo, and pin vocm need to be grou nded. note that pin vncm functions as the negative supply for the bias and v mid cell s, plus the logic interfaces , and should always be tied to ground. for optimal dynamic range, it is important that the inputs and outputs to both the driver amp lifier and t he preamplifier and the dga output amplifier be ac - coupled in a single - supply application. in figure 64, the dac and adc are presumed to operate on a 1.8 v or 3.3 v supply with a corresponding limited output and input swing. the da c outputs are currents that point down and generate a voltage in the 50 resistors that are connected to ground. the max imum voltage with a peak dac output current of 15 ma is 0.75 v; if a dac with a 20 ma peak current is used , th e n the maximum voltage is 1 v per side for a differential input signal of 2 v p - p . the driver amp lifier supports a 3 v p - p output swing on a 3.3 v supply . b ecause of its gain of 1.5 , the max imum input swing is 2 v p - p. the corresponding maximum output swing for the dga is 2.4 v p - p differential; the input to the preamplifier can be a maximum of 0.6 v p - p .
data sheet ad8260 rev. b | page 21 of 32 32 2 3 6 31 30 1.5k ? 1k ? 29 27 26 25 1k? 1.5k ? gm 9 24 23 22 21 vmid 4 1 1 ad8260 vmdo txen vmdi vncm vpsb enbl vgap vgan vngr vpsr gns3 gns2 gns1 gns0 prao vngr vocm inpp inrp inrn inpn txfb vneg vneg txop txop vpos vpos vpsr vmdo prai fdbk 07192-053 50 ? 0.1f 0.1f 0v, 1.8v/3.3v 0v, 1.8v/3.3v 5 3.3v 7 8 0.1f 0.1f 1.8v or 3.3v adc fs input 2v p-p inp inn 10 3.3v 11 12 13 14 16 15 17 18 19 rfb1 100 ? rfb2 100 ? 0.1f 20 3.3v 0.1f 0.1f powerline cable, etc. optional clamp diodes and snubbing resistors 0.1f 0.1f 50? 1.8v or 3.3v 20ma dac 1v max with 200ma pk bias attenuator gm stages logic 28 c fb optional user selected c fb reduces hf peaking with capacitive loading low-pass aa filter +? figure 64. block diagram and basic application connections high current driver amplifier the high current driver amplifier can deliver very large output currents suitable for driving complex impedances, such as a power line, a 50 line, or a coaxial cable. the input of the amplifier is fully differential and intended to be driven by a differential current-output dac, as shown in figure 64. the differential input signal is amplified by 1.5 and produces a 2.25 v p-p single-ended output signal from a 1.5 v p-p input signal. a dac with 15 ma maximum output current into a 50 load provides 1.5 v p-p of input voltage and results in 2.25 v p-p at the output. a dac whose output is 20 ma produces an output swing of 3 v p-p (neglecting a small gain error when driving the parallel combination of the 50 load-resistor and the internal 1 k gain resistor of the ad8260). for a 3.3 v supply rail, the maximum limit of the output voltage is 3 v p-p and distorts severely if exceeded. the recommended output for optimum distortion is 2 v p-p for a 3.3 v supply. correspondingly, larger output swings are accommodated for higher supply voltages such as +5 v or 5 v. for optimum distortion, the input drive must be controlled such that the output swing is well within saturation levels established by the supply rail. the output swing can be reduced by using load resistors with values less than 50 or by reducing the amplifier gain by connecting external resistors in parallel with the internal 1 k and 1.5 k resistors between pin 27, pin 28, and pin 29, and between pin 30, pin 31, and pin 32. coincidently, noise is reduced because the gain setting resistors are the primary noise sources of the high current driver amplifier. the output-referred noise is 14 nv/ ? hz, of which 11 nv/ ? hz is due to the gain setting resistors. matching of the gain setting resistors is important for good common-mode rejection and the accuracy of the differential gain. if external resistors are used, their accuracy should be at least 1%. how low the resistor values can be is primarily determined by the quality of the ac ground at pin vocm; as the gain setting resistors decrease in value, the dynamic current increases, and the quality of the decoupling capacitors needs to increase correspondingly.
ad8260 data sheet rev. b | page 22 of 32 precautions to be observed during half- duplex operation during receive, when the high current driver-amplifier is disabled, its gain setting resistors provide a signal path from input to output. to prevent inadvertent dac signals from being transmitted while receiving via the preamplifier and dga, the dac in figure 64 must have no output signal. during transmit, the preamplifier and vga should be disabled through any of the nongain-setting codes (see table 4). vmid buffer the vmid buffer is a dc bias source that generates the voltage on pin 1 and pin 19, vmdo. node vmdo cannot accommodate large dynamic currents and requires excellent ac decoupling to ground. a high quality 0.1f capacitor located as close as possible to pin 1 and pin 19 (see figure 64) is normally sufficient to decouple the high values of current from node vmdo. when operating with dual power supplies, the buffer is disabled by connecting pin vmdi, pin vocm, and pin vmdo to ground. because the logic decoder in the dga (gnsx inputs) requires 3.3 v of headroom, the positive supply rails must be 3.3 v or greater whether single-ended or dual. if a dual supply is used, the negative rails are the same magnitude (opposite polarity) as the positive, that is, ?3.3 v when vpos, vpsb, and vpsr are +3.3 v. preamplifier the ad8260 includes an uncommitted current feedback op amp to buffer the resistive attenuator of the dga. external resistors are used to adjust the gain. the preamplifier is characterized with a noninverting gain of 6 db (2) and both gain resistor values of 100 . the preamplifier gain can be increased using different gain ratios of r fb1 and r fb2 , trading off bandwidth and offset voltage. the sum of the values of r fb1 and r fb2 should be 200 to maintain low distortion. r fb2 should be 100 because it and an internal compensation capacitor determine the ?3 db bandwidth of the amplifier. smaller resistor values may compromise preamplifier stability. because the ad8260 is internally dc-coupled, larger preamplifier gains increase its offset voltage. the circuit contains an internal bias resistor and some offset compensation; however, if a lower value of offset voltage is required, it can be compensated by connecting a resistor between the fdbk pin and the supply voltage. if the offset is negative, the resistor value connects to the negative supply; otherwise, it connects to the positive supply. for larger gains, the overall noise is reduced if a low value of r fb1 is selected. for values of r fb1 = 20 and r fb2 = 301 , the preamplifier gain is 16 (24.1 db) and the input-referred noise is about 1.5 nv/hz. for this value of gain, the overall gain range increases by 18 db so that the absolute gain range is 12 db to 42 db. preamplifier noise the total input-referred voltage and current noise of the positive input of the preamplifier is about 2.4 nv/ ? hz and 5 pa/ ? hz, respectively. the dga output referred noise is about 25 nv/ ? hz at low gains and 39 nv/ ? hz at the highest gain. the 25 nv/ ? hz divided by the dga fixed gain of 8 results in 3.12 nv/ ? hz referred to the dga input. note that this value includes the noise of the dga gain setting resistors as well. if this voltage is divided by the preamplifier gain of 2, the dga noise referred all the way to the preamplifier input is about 1.56 nv/ ? hz. from this, it can be determined that the preamplifier, including the 100 gain setting resistors, contributes about 1.8 nv/ ? hz. the two 100 resistors each contribute 1.29 nv/ ? hz at the output of the preamplifier and 0.9 nv/ ? hz referred to the input. with the gain resistor noise subtracted, the preamplifier noise alone is about 1.6 nv/ ? hz. equation 1 shows the calculation that determines the output- referred noise at maximum gain (24 db or 16). ?? 2 , 2 , 2 1 2 , 2 , 2 , 2 , ) () () ()()( vga vgan vga rfb2n vga fb fb rfb1n spran t pran t rsn outn aeaea r r eriaeaee ????????????? ? (1) where: a t is the total gain from preamplifier input to the vga output. e n , rs is the noise of the source resistance. e n,pra is the input-referred voltage noise of the preamplifier. i n,pra is the current noise of the preamplifier at the prai pin. r s is the source resistance. a vga is the vga gain. e n,rfb1 is the voltage noise of r fb1 . e n,rfb2 is the voltage noise of r fb2 . e n,vga is the input-referred voltage noise of dga (low gain output-referred noise divided by a fixed gain of 8).
data sheet ad8260 rev. b | page 23 of 32 assuming r s = 0, r fb1 = r fb2 = 100 , a t = 16, and a vga = 8, the noise simplifies to hz/nv39 )812.3()829.1(2)166.1( 2 2 2 ??????? ? outn e (2) taking this result and dividing by 16 gives the total input-referred noise with a short-circuited input as 2.4 nv/ ? hz. when the preamplifier is used in the inverting configuration with the same r fb1 = r fb2 = 100 as in the previous example, then e n-out does not change; however, because the gain decreases by 6 db, the input-referred noise increases by a factor of 2 to about 4.8 nv/ ? hz. the reason for this is that the noise gain to the dga output of all the noise generators stays the same, but the preamp inverting gain is (?1) compared to the (+2) in the noninverting configuration. this doubles the input-referred noise. dga referring to figure 64, the signal path consists of a 30 db programmable attenuator followed by a fixed gain amplifier of 18 db for a total dga gain range of ?12 db to +18 db. with the preamplifier configured for a gain of 6 db, the composite gain range is ?6 db to +24 db from single-ended preamplifier input to differential dga output. the dga plus preamplifier with 6 db of gain implements the following gain law: )db( 01.3)db( icpt code code db gain ? ? ? ? ? ? ? ? ? where: icpt is the nominal intercept, ?9 db. code values are decimal from 1 to 11. the icpt increases as the gain of the preamplifier is increased. for example, if the gain of the preamplifier is increased by 6 db, then icpt increases to ?3 db. gain control to change the gain, the desired four bits are programmed on pin gns0 to pin gns3, where gns0 is the lsb (d0) and gns3 is the msb (d3). the states of decimal 0 and decimal 12 through decimal 15 disable the preamplifier (pra) and dga (see table 4). table 4. gain control logic table d3 d2 d1 d0 function comments 0 0 0 0 disable pra and dga powered down 0 0 0 1 ?6 the numbers in the function column are composite gain values in db for the corresponding code, when the preamplifier gain is 6 db. for other values of preamplifier gain, the gain is amended accordingly; for example, if the preamplifier gain is 12 db, the gain values increase by 6 db. when using the dga single ended, the composite gain decreases by 6 db. 0 0 1 0 ?3 0 0 1 1 0 0 1 0 0 3 0 1 0 1 6 0 1 1 0 9 0 1 1 1 12 1 0 0 0 15 1 0 0 1 18 1 0 1 0 21 1 0 1 1 24 1 1 0 0 disable pra and dga powered down 1 1 0 1 disable pra and dga powered down 1 1 1 0 disable pra and dga powered down 1 1 1 1 disable pra and dga powered down output stage the gain of the voltage feedback output stage is fixed at 18 db and inaccessible to the user. otherwise, it is similar to the preamplifier in speed and bandwidth. the overall ?3 db bandwidth of the preamplifier and dga combination is 230 mhz. attenuator the input resistance of the vga attenuator is nominally 265 . assuming that the default preamplifier feedback network of r fb1 and r fb2 is 200 , the effective preamplifier load is about 114 . the attenuator is composed of ten 3.01 db sections for a total attenuation span of ?30.10 db. following the attenuator is a fixed gain amplifier with 18 db (8) gain. because of this relatively low gain, the output offset is less than 20 mv over the operating temperature range; the offset is largest at maximum gain because the preamplifier offset is amplified. the vmdo pin defines the common-mode reference for the input and output. the voltage at vmid is half the supply voltage for single-supply operation and 0 v when dual supplies are used.
ad8260 data sh eet rev. b | page 24 of 32 single - supply operation and ac coupling when operating the ad8260 from a single supply, there are two bias options for vmdo. ? use an external low impedance midpoint reference at p in vmdo and pull vmdi to vncm to shut down the vmid buffer. ? use the internal vmid buffer as shown in figure 64. in both cases, decoupling cap acitors are need ed on pin vmdo to absorb the dynamic currents. during single - supply operat ion , the preamplifier input is normally ac - coupled. an internal bias resistor (nominally 1 k ) connected between prai and vmdo provides bias to the preamplifier input pin. a 50 resistor connected bet ween pin prai and pin vmdo , in parallel with the internal 1 k , serves as a termin a - tion resistor and at the same time reduces the offset; the res ult is a composite value of about 48 . the vga input is biased through the attenu ator network and the voltage at pin vmdo. when active, t he vmid buffer provide s the needed bias currents . when the buffer is disabled , an external voltage is required at pi n vmdo to provide the bias currents. for exam ple , for a single 5 v application , a reference such as the adr43 and a stable op amp provide an adequate 2.5 v vmdo source. power - up/ power - down sequence for glitch - free power - up operation , the following power - up and power - down sequence is recommended: 1. enable the bias by pulling the enbl pin high . maintain gns0 to gns 3 and txen at ground. 2. i t is assumed that after the part wakes up from sleep mode, the receive section ( p reamplifier and dga) needs to be active first to listen to any signals , and the driver needs to be off. there fore , the gain code should b e set to 0001 ( ? 6 db of gain) first and then the gain adjusted as neede d. note that any code besides 1 to 11 (binary) disables the receive section ( see table 4 ). during receive , it is also important that the dac that provides the signal for the high current driver be disabled to avoid interfering with the received signal. 3. after receive , presumably data needs to be transmitted via the high c urrent driver amplifier. at this point, the dac should still be off. pull pin txen high and allow the high current driver to se ttle . enable the dac . although the preamplifier and dga can remain enabled during the previous sequence , there may be significant preamplifier overdrive , and it is best th at the receiver be disabled while transmitting. 4. pull pin enbl low to d isabl e the chip . to achieve the specified sleep current of 35 a , all logic pins must be pulled low as well. logic interfaces all logic pins use the same interfaces and , therefore , have the same behavior and thresholds. th e interface contains a schmitt t rigger type input with a threshold at about 1.1 v and a hystere - sis of 0.2 v. therefore, the logic l ow is between ground and 0.8 v, and logic h ig h is from 1.4 v to vpos. because the threshold is so low, the logic interfaces can be driven directly from 1.8 v or 3.3 v cmos. the input bias current is nominally 0.2 a when the applied voltage is 3.3 v and 18 na when grounded.
data sheet ad8260 rev. b | page 25 of 32 applications information the ad8260 is ideally suited for compact applications requiring high frequency and large current drive of complex modulation products. because the driver is capable of providing up to 300 ma (using a 3.3 v supply rail) to very low impedance loads, undefined network impedances are of little consequence. such applications can include, but are not limited to, local power line wiring found in homes or in automobiles, or low impedance complex filters used in communications. pulse response performance with loading effects are illustrated by various curves in the typical performance characteristics section. figure 65 is an application block diagram showing ad8260 devices configured as transceivers in a small local network. in this figure, consider a small security system consisting of a master controller and four satellite cameras. for example, the master can be a processor-controlled switch that routes data to and from local satellite cameras. the cameras video signals are modulated for transmission over an existing power system such as the wiring found in homes or small businesses. using the existing power network in this way eliminates the need to install additional cabling, thereby saving cost. portability is also achieved because the system can be moved to other locations should the need arise, simply by unplugging a satellite and moving it elsewhere. the ad8260 transceivers perform the same function at the master and slave locations; a high frequency current-output dac converts digital-to-analog data for the high current driver for transmission over a low impedance load. the input of the vga/preamplifier connects to the same load, functioning as the receiver. in such a system, multiple ad8260 devices are connected to form a network, much like a lan, except using the power-line wiring in a home or automobile in lieu of a cat-5 cable, for example. local power wiring coupling dac adc microprocessor + modulator microprocessor + modulator microprocessor + modulator controller satellite cameras coupling dac adc camera ad8260 ad8260 ad8260 coupling dac adc camera 07192-065 figure 65. ad8260 transceiver application figure 66 shows the ad8260 as a low distortion, high power driver. the vga and high current driver are combined by simply connecting the differential output of the vga directly to the input of the driver. a d8260 dac complex low z filter 10 ? vga/ preamplifier high current driver 0 7192-066 figure 66. ad8260 used as a vga driving a low impedance load
ad8260 data sheet rev. b | page 26 of 32 evaluation board analog devices provides evaluation boards to customers as a support service so that the circuit designer can become familiar with the device in the most efficient way possible. the ad8260 evaluation board provides a fast, easy, and convenient means to assess the performance of the ad8260 before going through the inconvenience and expense of design and layout of a custom board. the board is shipped fully assembled and tested and provides basic functionality as shipped. connectors enable the user to connect standard types of lab test equipment without having to wait for the rest of the design to be completed. figure 67 shows a digital image of the top view and figure 70 shows the schematic. pcb artwork for all conductor and silkscreen layers is shown in figure 71 through figure 76. a description of a typical test setup is explained in the connecting the evaluation board section. the artwork can be used as a guide in circuit layout and parts placement. this is particularly useful for multiple function circuits with many pins, requiring multiple passive components. the board is shipped with the device fully enabled. moving the enable jumper to its upper position on the board disables the device. when the tx_en jumper is in its upper position, the high current driver is disabled. 07192-067 figure 67. top view of the ad8260 -evalz
data sheet ad8260 rev. b | page 27 of 32 connecting the evaluation board figure 69 shows an evaluation board with typical test connec- tions. the various pieces of test equipment are representative, and equivalent equipment may be substituted. the ad8260 includes two amplifier channels: a high current driver and a digitally controlled vga that is independently enabled. the slide switch labeled enable functions as the chip enable, the gnsx switches permit the preamplifier/vga to operate, and the tx_en switch enables the high current driver. these independent enable functions permit the device to operate in a send or listen mode when used as a transceiver. the high current driver features differential inputs and is optimally driven by a differential signal source. the input signal is monitored at the 2-pin header labeled inp, using a differential probe such as the tektronix p6247 (not shown). two 49.9 resistors are provided (r12 and r13), either for terminating coaxial cables from a signal generator or to be used as load resistors for a dac with a current source output. an optional external load resistor is connected at the sma connector txop and the output signal monitored at the 2-pin header labeled txop_1. as shipped, the gain of the high current driver is 1.5, its default value. the internal differential network with resistor values of 1 k and 1.5 k establishes this value. other values of gain are realized by connecting external resistors to the device at pin 23, pin 24, pin 27, pin 28, and pin 31, as shown in figure 68, which shows the internal structure for the default gain and how the gain can be modified. c comp inpp inrp vocm txfb inrn inpn txop txop vmdo 1k ? 1k ? 1.5k ? default gain setting components are shown in black, optional components are shown in gray. 1.5k ? + ? 29 27 23 24 30 32 1 31 28 07192-068 figure 68. gain-setting resistor s of the high current driver the vga/preamplifier is completely independent of the high current driver and features a single-ended input at the sma connector prai. the input signal is monitored at the header vpre_in. the output is monitored at the 2-pin header vga_out. the gain bits, gns0 through gns3, must be set before the vga/preamplifier can operate. table 4 lists the binary gain codes. the board is shipped with both enables (enbl and txen) engaged and the gain-code switches adjusted for maximum dga gain (1011). resistor r5 and resistor r6 establish the preamplifier gain and are 100 as shipped for a noninverting preamplifier gain of 2.
ad8260 data sheet rev. b | page 28 of 32 07192-057 power supply +5 v -5 v high current driver output function generator for vga input high current driver inputs vga output (to scope) single- ended vga input r load pulse generator with differential output figure 69. typical evaluation board connections
data sheet ad8260 rev. b | page 29 of 32 07192-070 ? vs +vs ?vs +vs inpp vpsr gns3 gns2 gns1 gns0 prao inrp inrn inpn txfb vneg u1 ad8260 29303132 28 25 26 27 vocm vneg vpsb vgan vgap enbl vncm vmdo txen vmdi 8 7 6 5 1 4 3 2 fdbk vmdo prai txop vpos vpsr vpos txop 20 17 18 19 21 22 23 24 1413 91 2 1110 15 16 vngr vngr gnd4 gnd3 gnd2 txop r9 0 ? r7 0 ? r21 0 ? l7 120nh fb ?vs r14 dni gnd6 gnd5 gnd c19 0.1f c18 0.1f c8 0.1f c17 0.1f c1 0.1f c2 0.1f c9 0.1f inrp inrn r12 49.9 ? r13 49.9 ? inr inp gnd1 c3 10f c4 10f + + vmdo c14 0.1f r20 0 ? l4 120nh fb c20 0.1f ?vs r3 dni +vs l6 120nh fb l5 120nh fb c6 0.1f c7 0.1f c5 0.1f r6 100 ? r5 100 ? prai r10 49.9 ? r11 453 ? c11 0.1f c12 0.1f c21 0.1f vpre_in vpre_out prao gns0 gns1 gns2 gns3 h l r19 0 ? c22 0.1f c16 0.1f +vs l3 120nh fb l2 120nh fb ?vs r4 dni dis vmdi l1 120nh fb en txen vpsb tx_en c15 0.1f c13 0.1f vpsb vps dis en enable vgan vgap r2 453 ? r1 453 ? vga _ out enbl c23 0.1f c10 0.1f r16 dni r17 dni r15 dni r18 dni txop_1 figure 70. ad8260 evaluation boardschematic diagram
ad8260 data sheet rev. b | page 30 of 32 07192-071 figure 71. ad8260-evalz component side assembly 07192-060 figure 72. ad8260-evalz component side copper 07192-061 figure 73. ad8260-evalz secondary side copper 07192-062 figure 74. ad8260-evalz power plane
data sheet ad8260 rev. b | page 31 of 32 07192-063 figure 75. ad8260-evalz ground plane 07192-064 figure 76. ad8260-evalz component side silkscreen
ad8260 data sheet rev. b | page 32 of 32 outline dimensions 1 0.50 bsc bottom view top view pin 1 indicator 32 9 16 17 24 25 8 exposed pad p i n 1 i n d i c a t o r seating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.20 min 2.85 2.70 sq 2.55 compliant to jedec standards mo-220-whhd-2. 08-22-2013-a pkg-004332 figure 77. 32-lead lead frame chip scale package [lfcsp] 5 mm 5 mm body and 0.75 mm package height (cp-32-21) dimensions shown in millimeters ordering guide model 1 temperature package description package option ad8260acpz-r7 ?40c to +105c 32-lead lead frame chip scale package [lfcsp] cp-32-21 ad8260acpz-rl ?40c to +105c 32-lead lead frame chip scale package [lfcsp] cp-32-21 ad8260acpz-wp ?40c to +105c 32-lead lead frame chip scale package [lfcsp] cp-32-21 ad8260-evalz evaluation board 1 z = rohs compliant part. ?2008C2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07192-0-5/16(b)

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